An electronic system design may incorporate any number of configurable or programmable logic devices, such as programmable logic devices (PLDs) or field programmable gate arrays (FPGAs). PLDs and FPGAs can be used to implement any logical function, for example, that an ASIC could perform. Additionally, PLDs and FPGAs are reconfigurable so as to allow updating of various programmable functions as needed. For example, FPGAs contain programmable logic elements and configurable and reconfigurable interconnects that allow the logic elements to be arranged together into different configurations to perform various functions. The logic elements generally also include memory elements, which may be simple flip-flops or more complete blocks of memory.
Some of the logic elements have asynchronous resets. However, asynchronous resets can create many problems in system design and optimization. For example, asynchronous resets can be difficult to merge with logic elements during logic synthesis. Thus, in some cases, it may be desirable to reduce the use of asynchronous resets in a design. Accordingly, it can be beneficial to provide a mechanism to address the aforementioned problems.